even wat gekopieerd:
link:
http://china.xilinx.com/ipcenter/processor...edded/timer.htm
PowerPC Architecture - Timer
The PowerPC 405 contains a 64-bit time base and three timers. The time base is incremented synchronously using the CPU clock or an external clock source. The three timers are incremented synchronously with the time base. The three timers supported by the PowerPC 405 core are:
Programmable Interval Timer (PIT)
Fixed Interval Timer (FIT)
Watchdog Timer (WDT)
The Programmable Interval Timer (PIT) is a 32-bit register that is decremented at the time base increment frequency. The PIT register is loaded with a delay value. When the PIT count reaches 0, a PIT interrupt occurs. Optionally, the PIT can be programmed to automatically reload the last delay value and begin decrementing again.
The Fixed Interval Timer (FIT) causes an interrupt when a selected bit in the time-base register changes from 0 to 1. Programmers can select one of four predefined bits in the time base for triggering a FIT interrupt.
The Watchdog Timer (WDT) causes a hardware reset when a selected bit in the time base register changes from 0 to 1. Programmers can select one of four predefined bits in the time base for triggering a reset and can define the type of reset.
Deze link geeft ook veel informatie:
http://www.mvps.org/directx/articles/selec...r_functions.htm
Een computertaal is voor mensen, niet voor de computer.